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<a href="#nested-classes">Data Structures</a> &#124;
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<p>Chip-specific PLL definitions.  
<a href="#details">More...</a></p>
<div class="textblock"><code>#include &lt;avr32/io.h&gt;</code><br/>
<code>#include &lt;osc.h&gt;</code><br/>
<code>#include &lt;stdbool.h&gt;</code><br/>
<code>#include &lt;stdint.h&gt;</code><br/>
</div>
<p><a href="uc3c_2pll_8h_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structpll__config.html">pll_config</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Hardware-specific representation of PLL configuration.  <a href="structpll__config.html#details">More...</a><br/></td></tr>
<tr><td colspan="2"><h2><a name="define-members"></a>
Defines</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="uc3c_2pll_8h.html#a07643f13da0314cb5324f12c11f326dd">AVR32_SCIF_PLL_VCO_RANGE0_MAX_FREQ</a>&#160;&#160;&#160;240000000</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="uc3c_2pll_8h.html#aabe42b8f766d0b3a02385d4c04494810">AVR32_SCIF_PLL_VCO_RANGE0_MIN_FREQ</a>&#160;&#160;&#160;160000000</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="uc3c_2pll_8h.html#ac443c8c74126291df314757d411a14f5">AVR32_SCIF_PLL_VCO_RANGE1_MAX_FREQ</a>&#160;&#160;&#160;180000000</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="uc3c_2pll_8h.html#a39aa078b560b8e913eb40001f6a857ca">AVR32_SCIF_PLL_VCO_RANGE1_MIN_FREQ</a>&#160;&#160;&#160;80000000</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#ga3778ecbe3fb3e8480ce23312a613a0aa">PLL_TIMEOUT_MS</a>&#160;&#160;&#160;div_ceil(1000 * (PLL_MAX_STARTUP_CYCLES * 2), OSC_RCSYS_MIN_HZ)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of milliseconds to wait for PLL lock.  <a href="group__pll__group.html#ga3778ecbe3fb3e8480ce23312a613a0aa"></a><br/></td></tr>
<tr><td colspan="2"><div class="groupHeader">Chip-specific PLL characteristics</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#ga3a7cd8f570834e0f208037619b798aef">PLL_MAX_STARTUP_CYCLES</a>&#160;&#160;&#160;((1 &lt;&lt; AVR32_SCIF_PLL_PLLCOUNT_SIZE) - 1)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum PLL startup time in number of slow clock cycles.  <a href="group__pll__group.html#ga3a7cd8f570834e0f208037619b798aef"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#ga23ebd75638f609ce613b82e773ea48a5">NR_PLLS</a>&#160;&#160;&#160;2</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of on-chip PLLs.  <a href="group__pll__group.html#ga23ebd75638f609ce613b82e773ea48a5"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#ga58acd4425beaa32dad5ccffa073cb0a5">PLL_MIN_HZ</a>&#160;&#160;&#160;40000000</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Minimum frequency that the PLL can generate.  <a href="group__pll__group.html#ga58acd4425beaa32dad5ccffa073cb0a5"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#gaeced77fb7ec635ab33085a71a0c15227">PLL_MAX_HZ</a>&#160;&#160;&#160;240000000</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum frequency that the PLL can generate.  <a href="group__pll__group.html#gaeced77fb7ec635ab33085a71a0c15227"></a><br/></td></tr>
<tr><td colspan="2"><div class="groupHeader">Chip-specific PLL options</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#ga03717c32c87c59df4b94a4233a5c2e3e">PLL_OPT_VCO_RANGE_LOW</a>&#160;&#160;&#160;0</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">VCO frequency range is 80-180 MHz (160-240 MHz if unset).  <a href="group__pll__group.html#ga03717c32c87c59df4b94a4233a5c2e3e"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#ga0ab4eb3395991501ba1c8aa8a7c606be">PLL_OPT_OUTPUT_DIV</a>&#160;&#160;&#160;1</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Divide output frequency by two.  <a href="group__pll__group.html#ga0ab4eb3395991501ba1c8aa8a7c606be"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#gaa2d0c945bda195002b421eb79d2c87ca">PLL_OPT_WBM_DISABLE</a>&#160;&#160;&#160;2</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable wide-bandwidth mode.  <a href="group__pll__group.html#gaa2d0c945bda195002b421eb79d2c87ca"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#gae74457d5b4073fdb82cb6b9f3d8b76e2">PLL_NR_OPTIONS</a>&#160;&#160;&#160;AVR32_SCIF_PLL_PLLOPT_SIZE</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of PLL option bits.  <a href="group__pll__group.html#gae74457d5b4073fdb82cb6b9f3d8b76e2"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#ga49eaeabf6add7c1be4000c77cb8b2bff">PLL_VCO_LOW_THRESHOLD</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">The threshold under which to set the <a class="el" href="group__pll__group.html#ga03717c32c87c59df4b94a4233a5c2e3e" title="VCO frequency range is 80-180 MHz (160-240 MHz if unset).">PLL_OPT_VCO_RANGE_LOW</a> option.  <a href="group__pll__group.html#ga49eaeabf6add7c1be4000c77cb8b2bff"></a><br/></td></tr>
<tr><td colspan="2"><h2><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#gacfb06d8fc0ffbe934077438884ae697f">pll_source</a> { <a class="el" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa060f32d7388cf128f527739090aa4217">PLL_SRC_OSC0</a> =  0, 
<a class="el" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa28e003235f43b85c6ee49bbe81b67218">PLL_SRC_OSC1</a> =  1, 
<a class="el" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa87507b481d2c92b721d802a5ae6cc8a5">PLL_SRC_RC8M</a> =  2, 
<a class="el" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa5020b47784b860efae2c423d33999dcc">PLL_NR_SOURCES</a>
 }</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL clock source.  <a href="group__pll__group.html#gacfb06d8fc0ffbe934077438884ae697f">More...</a><br/></td></tr>
<tr><td colspan="2"><h2><a name="func-members"></a>
Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#gaeee0be729bfa596c973cf6f725a89d45">pll_config_write</a> (const struct <a class="el" href="structpll__config.html">pll_config</a> *cfg, unsigned int pll_id)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Activate the configuration <em>cfg</em> on <em>pll_id</em>.  <a href="group__pll__group.html#gaeee0be729bfa596c973cf6f725a89d45"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#gaede6e280289cb0759af0f5a34f5a627f">pll_enable</a> (const struct <a class="el" href="structpll__config.html">pll_config</a> *cfg, unsigned int pll_id)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Activate the configuration <em>cfg</em> and enable PLL <em>pll_id</em>.  <a href="group__pll__group.html#gaede6e280289cb0759af0f5a34f5a627f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#ga9b369b5f673b10a6adf14cd3c9fea5ad">pll_disable</a> (unsigned int pll_id)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the PLL identified by <em>pll_id</em>.  <a href="group__pll__group.html#ga9b369b5f673b10a6adf14cd3c9fea5ad"></a><br/></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interaction with the PLL hardware</div></td></tr>
<tr><td colspan="2"><h2><a name="member-group"></a>
PLL configuration</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#ga16c8db5e3f1a2c759a88371120579c4d">pll_get_default_rate</a>(pll_id)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the default rate in Hz of <em>pll_id</em>.  <a href="group__pll__group.html#ga16c8db5e3f1a2c759a88371120579c4d"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pll__group.html#ga2b9ba9ce6a7290303f6e8d41191fd0d8">pll_config_defaults</a>(cfg, pll_id)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize PLL configuration using default parameters.  <a href="group__pll__group.html#ga2b9ba9ce6a7290303f6e8d41191fd0d8"></a><br/></td></tr>
</table>
<hr/><a name="details" id="details"></a><h2>Detailed Description</h2>
<div class="textblock"><p>Chip-specific PLL definitions. </p>
<p>Copyright (C) 2010 - 2011 Atmel Corporation. All rights reserved. </p>
</div><hr/><h2>Define Documentation</h2>
<a class="anchor" id="a07643f13da0314cb5324f12c11f326dd"></a><!-- doxytag: member="uc3c/pll.h::AVR32_SCIF_PLL_VCO_RANGE0_MAX_FREQ" ref="a07643f13da0314cb5324f12c11f326dd" args="" -->
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define AVR32_SCIF_PLL_VCO_RANGE0_MAX_FREQ&#160;&#160;&#160;240000000</td>
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<a class="anchor" id="aabe42b8f766d0b3a02385d4c04494810"></a><!-- doxytag: member="uc3c/pll.h::AVR32_SCIF_PLL_VCO_RANGE0_MIN_FREQ" ref="aabe42b8f766d0b3a02385d4c04494810" args="" -->
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define AVR32_SCIF_PLL_VCO_RANGE0_MIN_FREQ&#160;&#160;&#160;160000000</td>
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<a class="anchor" id="ac443c8c74126291df314757d411a14f5"></a><!-- doxytag: member="uc3c/pll.h::AVR32_SCIF_PLL_VCO_RANGE1_MAX_FREQ" ref="ac443c8c74126291df314757d411a14f5" args="" -->
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<div class="memproto">
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          <td class="memname">#define AVR32_SCIF_PLL_VCO_RANGE1_MAX_FREQ&#160;&#160;&#160;180000000</td>
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</div>
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<a class="anchor" id="a39aa078b560b8e913eb40001f6a857ca"></a><!-- doxytag: member="uc3c/pll.h::AVR32_SCIF_PLL_VCO_RANGE1_MIN_FREQ" ref="a39aa078b560b8e913eb40001f6a857ca" args="" -->
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          <td class="memname">#define AVR32_SCIF_PLL_VCO_RANGE1_MIN_FREQ&#160;&#160;&#160;80000000</td>
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